The present invention relates to a method for fabricating a semiconductor device, and more particularly, it relates to a method for forming a hole and an interconnect groove respectively for use in forming a plug and a buried interconnect by a dual damascene method.
Recently, there are increasing demands for attaining high performance and refinement of semiconductor integrated circuit devices. Therefore, as a method for increasing the information transfer rate within a semiconductor integrated circuit and improving the reliability of interconnects included in the semiconductor integrated circuit, the dual damascene method using copper as an interconnect material attracts attention.
A method for forming a hole and an interconnect groove in an insulating film for use in forming a plug and a buried interconnect by the dual damascene method is roughly divided into two, one of which is trench-first process for forming the interconnect groove first and the other of which is hole-first process for forming the hole first.
Since a hole is formed after forming an interconnect groove in an insulating film in the trench-first process, it is necessary to perform lithography for forming the hole in a region of the insulating film where the interconnect groove has been formed. At this point, since a level difference derived from the interconnect groove has been caused in a resist film, when the resist film is subjected to pattern exposure for forming the hole, the focus is disadvantageously shifted and hence a fine hole pattern cannot be formed. Accordingly, the hole-first process is preferred for forming a fine hole.
Now, a first conventional method for forming a hole and an interconnect groove by the hole-first process will be described with reference to FIGS. 12A through 12C and 13A through 13C.
First, as shown in FIG. 12A, a lower interconnect 12 is formed in a first insulating film 11 deposited on a semiconductor substrate 10, and thereafter, a passivation film 13 for preventing corrosion of the lower interconnect 12 is formed from a silicon nitride film with a comparatively large thickness on the first insulating film 11. The passivation film 13 has a comparatively large thickness because the passivation film 13 works as an etching stopper in two etching procedures described later.
Next, after depositing a second insulating film 14 on the passivation film 13, a patterned antireflection film 15 and a first resist pattern 16 are formed on the second insulating film 14. Then, the second insulating film 14 is etched by using the first resist pattern 16 as a mask, so as to form a hole 17A in the second insulating film 14. In this etching procedure, the passivation film 13 works as the etching stopper. Thereafter, the first resist pattern 16 and etching residues are removed by ashing and wet cleaning.
Subsequently, as shown in FIG. 12B, a second resist pattern 18 is formed on the antireflection film 15.
Then, the second insulating film 14 is etched by using the second resist pattern 18 as a mask, so as to form an interconnect groove 17B in the second insulating film 14 as shown in FIG. 12C. Also in this etching procedure, the passivation film 13 works as the etching stopper. Thereafter, the second resist pattern 18 and etching residues are removed by the ashing, and the substrate is cleaned.
Next, as shown in FIG. 13A, the passivation film 13 is etched by using, as a mask, the second insulating film 14 in which the hole 17A and the interconnect groove 17B have been formed, so as to expose the lower interconnect 12.
Then, as shown in FIG. 13B, a metal film 19 is deposited on the second insulating film 14 so as to fill the hole 17A and the interconnect groove 17B, and a portion of the metal film 19 present above the second insulating film 14 is removed by, for example, CMP. Thus, a plug 19A and an upper interconnect 19B made from the metal film 19 are formed as shown in FIG. 13C.
Now, a second conventional method for forming a hole and an interconnect groove by the hole-first process will be described with reference to FIGS. 14A through 14C and 15A through 15C.
First, as shown in FIG. 14A, a lower interconnect 22 is formed in a first insulating film 21 deposited on a semiconductor substrate 20, and thereafter, a passivation film 23 for preventing corrosion of the lower interconnect 22 is formed from a silicon nitride film with a comparatively small thickness on the first insulating film 21. The passivation film 23 has a comparatively small thickness because the passivation film 23 works as an etching stopper in one etching procedure alone as described later. Then, after depositing a second insulating film 24 on the passivation film 23, a patterned antireflection film 25 and a first resist pattern 26 are formed on the second insulating film 24. Next, the second insulating film 24 is etched by using the first resist pattern 26 as a mask, so as to form a hole 27A in the second insulating film 24. In this etching procedure, the passivation film 23 works as the etching stopper. Thereafter, the first resist pattern 26 and etching residues are removed by the ashing, and the substrate is cleaned.
Next, as shown in FIG. 14B, a second resist pattern 28 is formed on the antireflection film 25, and an organic film 29 made of a resist material or an antireflection film material is buried in the hole 27A. At this point, in the case where the organic film 29 is made of a resist material, after forming a resist film on the antireflection film 25 so as to fill the hole 27A, the resist film is patterned, so that the organic film 29 can be buried in the hole 27A. Alternatively, in the case where the organic film 29 is made of an antireflection film material, after burying the organic film 29 in the hole 27A, a resist pattern is formed on the antireflection film 25, so that the organic film 29 can be buried in the hole 27A.
Next, the second insulating film 24 is etched by using the second resist pattern 28 as a mask, so as to form an interconnect groove 27B in the second insulating film 24 as shown in FIG. 14C. In this etching procedure, the organic film 29 protects the lower interconnect 22. Then, the second resist pattern 28, the organic film 29 and etching residues are removed by the ashing, and the substrate is cleaned.
Subsequently, as shown in FIG. 15A, the passivation film 23 is etched by using, as a mask, the second insulating film 24 in which the hole 27A and the interconnect groove 27B have been formed, so as to expose the lower interconnect 22.
Then, as shown in FIG. 15B, a metal film 31 is deposited on the second insulating film 24 so as to fill the hole 27A and the interconnect groove 27B, and a portion of the metal film 31 present above the second insulating film 24 is removed by, for example, the CMP. Thus, a plug 31A and an upper interconnect 31B made from the metal film 31 are formed as shown in FIG. 15C.
In the first conventional method, the passivation film 13 has a large thickness in order to prevent the lower interconnect 11 from being damaged during the two etching procedures as described above.
Therefore, the passivation film 13, which is made from a silicon nitride film with a large dielectric constant and has a large thickness, is provided between the lower interconnect 11 and the upper interconnect 19B as shown in FIG. 13C. Accordingly, interconnect capacitance between the lower interconnect 11 and the upper interconnect 19B is disadvantageously large, which can cause a problem of signal delay.
Furthermore, since the passivation film 13 is largely etched in the etching procedure for exposing the lower interconnect 11, a damage layer 12a is unavoidably formed in the lower interconnect 11 as shown in FIG. 13A, which disadvantageously spoils the reliability of the lower interconnect 11.
Moreover, since the passivation film 13 is largely etched in the etching procedure for exposing the lower interconnect 11, the interconnect groove 17B has a round shoulder in its uppermost wall as shown in FIG. 13A. When the interconnect groove 17B has a round shoulder in the uppermost wall, the metal film 19 filled in the round shoulder portion of the interconnect groove 17B may cause a short-circuit between adjacent interconnect grooves 19B.
On the other hand, in the second conventional method, the passivation film 13 has a small thickness and hence the above-described problems of the first conventional method can be avoided, but other problems as described below occur.
Since the organic film 29 is buried in the hole 27A as shown in FIG. 14B, a portion of the second insulating film 24 in contact with the organic film 29 is difficult to etch in the etching procedure for forming the interconnect groove 27B. Therefore, a fence 24a of the second insulating film 24 is formed between the hole 27A and the interconnect groove 27B as shown in FIG. 14C. Accordingly, a broken piece 32 of the fence 24a and a particle 33 of the organic film 29 are generated on the antireflection film 25 as shown in FIG. 15A. Therefore, when the plug 31A and the upper interconnect 31B are formed by removing the portion of the metal film 31 present above the second insulating film 24 by the CM1, a scratch 25a is caused on the top face of the antireflection film 25 as shown in FIG. 15C, which can disadvantageously cause disconnection of the upper interconnect 31B. Alternatively, when the metal film 31 remains in the scratch 25a, a short-circuit can be caused between adjacent upper interconnects 31B.
Furthermore, since the fence 24a is present between the hole 27A and the interconnect groove 27B, the metal film 31 is insufficiently filled. Accordingly, a void 33 is formed in the upper interconnect 31B as shown in FIGS. 15B and 15C, which can disadvantageously lowers the reliability of the upper interconnect 31B.
As described so far, although the fence of the insulating film is not formed between the hole and the interconnect groove in the first conventional method, the passivation film should have a large thickness. In contrast, although the passivation film may have a small thickness in the second conventional method, the fence of the insulating film is unavoidably formed between the hole and the interconnect groove.
In consideration of the aforementioned conventional problems, an object of the invention is, in a method for fabricating a semiconductor device including a step of forming an interconnect groove continuous with a hole in an insulating film after forming the hole in the insulating film, preventing a fence of the insulating film from being formed in a boundary between the hole and the interconnect groove even when a passivation film present at the bottom of the hole has a small thickness.
In order to achieve the object, the first method for fabricating a semiconductor device of this invention includes the steps of depositing a peeling film on an insulating film, which is formed on a semiconductor substrate and has a hole, and on a bottom and a wall of the hole in such a manner that the hole is not filled with the peeling film; forming a resist film over the peeling film in such a manner that the hole is filled with the resist film; forming a resist pattern from the resist film by patterning the resist film in such a manner that an interconnect groove opening is formed around the hole and that a portion of the resist film remains within the hole; forming an interconnect groove continuous with the hole in the insulating film by etching the peeling film and the insulating film with the resist pattern used as a mask; and removing a remaining portion of the peeling film after removing the resist pattern.
In the first method for fabricating a semiconductor device, since the resist pattern present within the hole protects a lower interconnect in etching for forming the interconnect groove, the thickness of a passivation film formed on the lower interconnect can be small. Accordingly, the interconnect capacitance between the lower interconnect and an upper interconnect can be reduced, the reliability of the lower interconnect can be improved because a damage layer is prevented from being formed in the lower interconnect, and the interconnect groove minimally has a round shoulder in its uppermost wall so as to avoid a short-circuit between adjacent upper interconnects.
Furthermore, a fence of the insulating film is not formed in a boundary between the hole and the interconnect groove, and the peeling film in which a fence has been formed is ultimately removed. Therefore, a broken piece of a fence is not generated and a metal film is definitely filled in the hole. As a result, the reliability of the upper interconnect can be improved.
The second method for fabricating a semiconductor device of this invention includes the steps of depositing a peeling film on an insulating film, which is formed on a semiconductor substrate and has a hole, and on a bottom and a wall of the hole in such a manner that the hole is not filled with the peeling film; forming an organic film on a portion of the peeling film within the hole; forming a resist pattern from a resist film, which is formed on the peeling film and the organic film, by patterning the resist film in such a manner that an interconnect groove opening is formed around the hole; forming an interconnect groove continuous with the hole in the insulating film by etching the peeling film and the insulating film with the resist pattern used as a mask; and removing a remaining portion of the peeling film after removing the resist pattern and the organic film.
In the second method for fabricating a semiconductor device, since the organic film present within the hole protects a lower interconnect in etching for forming the interconnect groove, the thickness of a passivation film formed on the lower interconnect can be small. Accordingly, the interconnect capacitance between the lower interconnect and an upper interconnect can be reduced, the reliability of the lower interconnect can be improved because a damage layer is prevented from being formed in the lower interconnect, and the interconnect groove minimally has a round shoulder in its uppermost wall so as to avoid a short-circuit between adjacent upper interconnects.
Furthermore, a fence of the insulating film is not formed in a boundary between the hole and the interconnect groove, and the peeling film in which a fence has been formed is ultimately removed. Therefore, a broken piece of a fence is not generated and a metal film is definitely filled in the hole. As a result, the reliability of the upper interconnect can be improved.
The third method for fabricating a semiconductor device of this invention includes the steps of depositing a peeling film on an insulating film, which is formed on a semiconductor substrate and has a hole, and on a bottom and a wall of the hole in such a manner that the hole is not filled with the peeling film; forming an organic film over the peeling film in such a manner that the hole is filled with the organic film; forming a resist pattern from a resist film, which is formed on the organic film, by patterning the resist film in such a manner that an interconnect groove opening is formed around the hole; forming an interconnect groove continuous with the hole in the insulating film by etching the peeling film and the insulating film with the resist pattern used as a mask; and removing a remaining portion of the peeling film after removing the resist pattern and the organic film.
In the third method for fabricating a semiconductor device, since the organic film present within the hole protects a lower interconnect in etching for forming the interconnect groove, the thickness of a passivation film formed on the lower interconnect can be small. Accordingly, the interconnect capacitance between the lower interconnect and an upper interconnect can be reduced, the reliability of the lower interconnect can be improved because a damage layer is prevented from being formed in the lower interconnect, and the interconnect groove minimally has a round shoulder in its uppermost wall so as to avoid a short-circuit between adjacent upper interconnects.
Furthermore, since a fence of the insulating film is not formed in a boundary between the hole and the interconnect groove and the peeling film in which a fence has been formed is ultimately removed, a broken piece of a fence is not generated and a metal film is definitely filled in the hole. As a result, the reliability of the upper interconnect can be improved.
In any of the first through third methods for fabricating a semiconductor device, a thickness of the peeling film is preferably 30% or less of a diameter of the hole.
In this manner, when the peeling film is deposited on the bottom and the wall of the hole so as not to fill the hole, the depth of etching for forming the interconnect groove cannot be too large and variation in the necessary groove depth can be small. As a result, variation in the interconnect resistance can be reduced.
In any of the first through third methods for fabricating a semiconductor device, it is preferred that the insulating film includes substantially neither a hydroxide nor a hydrate and the peeling film includes a hydroxide or a hydrate, and that the step of removing a remaining portion of the peeling film is performed by using vapor hydrofluoric acid.
Thus, a difference in the etching rate between the peeling film and the insulating film can be made large in the step of removing the remaining portion of the peeling film. Therefore, the side walls and the opening edges of the interconnect groove and the hole are touch to etch, so that the shape of the interconnect can be prevented from being spoiled due to side etching or the like. As a result, the reliability of the upper interconnect buried in the interconnect groove and the hole can be improved.
In any of the first through third methods for fabricating a semiconductor device, it is preferred that the peeling film is made from a BPSG film, and that the insulating film is made from a fluorine-containing silicon oxide film, a TEOS film, a silicon oxide nitrided film, a nondoped silicate glass film, a phosphorus-doped silicate glass film, a thermally oxidized film, a carbon-containing silicon oxide film or an organic-inorganic hybrid film.
Thus, a difference in the etching rate between the peeling film and the insulating film can be made large in the step of removing the remaining portion of the peeling film. Therefore, the side walls and the opening edges of the interconnect groove and the hole are touch to etch, so that the shape of the interconnect can be prevented from being spoiled due to the side etching or the like. As a result, the reliability of the upper interconnect buried in the interconnect groove and the hole can be improved.
In the case where the insulating film is made from a fluorine-containing silicon oxide film, a silicon oxide nitrided film, a carbon-containing silicon oxide film or an organic-inorganic hybrid film in any of the first through third methods for fabricating a semiconductor device, the present invention is particularly useful.
An insulating film made from a fluorine-containing silicon oxide film, a silicon oxide nitrided film, a carbon-containing silicon oxide film or an organic-inorganic hybrid film has a property to deactivate an acid generated from a chemically amplified resist. In the present invention, however, even when the resist pattern is made from a chemically amplified resist, an acid generated from the resist pattern is never deactivated because the peeling film is present between the insulating film and the resist pattern.
In any of the first through third methods for fabricating a semiconductor device, it is preferred that neither the insulating film nor the peeling film includes a metal element.
Thus, the variation in the etching depth in forming the interconnect groove can be reduced and a used etching chamber can be prevented from being contaminated with a metal.
In any of the first through third methods for fabricating a semiconductor device, the peeling film is preferably deposited by CVD.
Thus, even when the hole has a high aspect ratio, the peeling film can be easily and definitely deposited on the bottom and the wall of the hole without filling the hole, and the resultant peeling film minimally overhangs.
In the first method for fabricating a semiconductor device, the step of forming a resist film preferably includes a sub-step of allowing the resist film to thermally flow.
Thus, the resist film can be definitely filled in the hole.
Alternatively, in the second or third method for fabricating a semiconductor device, the step of forming an organic film preferably includes a sub-step of allowing the organic film to thermally flow.
Thus, the organic film can be definitely filled in the hole.